1. Field of the Invention
The present invention relates to a method for manufacturing a metal line of a semiconductor device, and in particular to an improved method for manufacturing metal line of semiconductor device wherein undesirable etching of an edge of an interlayer insulating film which causes electrical shorts between metal lines can be prevented.
2. Description of the Background Art
A semiconductor device includes a plurality of vertically stacked electrical wiring layers and connection layers connecting vertically stacked electrical wiring layers.
In case of logic devices, gates and metal layers correspond to the electrical wiring layers, and contact hole layers connecting gates and metal layers and via contact hole layers connecting upper and lower wiring layers correspond to the connection layers.
In accordance with a conventional method for manufacturing metal line of semiconductor device, a metal line is formed on a planarized surface and an interlayer insulating film planarizing the entire surface is then formed. However, this method is disadvantageous in that the patterning of metal lines having microscopic widths is very difficult.
A new method, namely a damascene method wherein a interlayer insulating film having a groove for metal line is formed on a planarized surface and the groove is filled with metal have been proposed to overcome the disadvantages of the conventional method, which is described hereinbelow.
FIGS. 1a through 1e are cross-sectional diagrams illustrating a conventional damascene method for manufacturing metal line of semiconductor device.
Referring to FIG. 1a, a lower structure such as a device isolation film (not shown) defining an active region, a word line (not shown), a bit line (not shown) and a capacitor (not shown) are formed on a semiconductor substrate (not shown). A lower insulating layer (not shown) is deposited to planarize the entire surface.
Thereafter, a lower metal line 11 connected to the lower structure is deposited on the lower insulating layer using copper. A first insulating film 13 exposing a top surface of the lower metal line 11 is then formed on the entire surface.
Next, a stacked structure of a first etch barrier film 15, a second interlayer insulating film 17, a second etch barrier film 19, a third interlayer insulating film 21 and a hard mask layer 23 is formed on the entire surface. The stacked structure is then etched via a photolithography process using metal line contact mask (not shown), i.e. via contact mask (not shown) to expose the first etch barrier film 15.
Now referring to FIG. 1b, an organic anti-reflection film 27 is deposited on the entire surface. Thereafter, a photoresist pattern 29 is formed on the organic anti-reflection film 27. The photoresist pattern 29 is formed via exposure and development process using metal line mask.
Referring to FIG. 1b, the organic anti-reflection film 27, the hard mask layer 23 and the third interlayer insulating film 21 are etched using the photoresist pattern 29 as a mask to expose the second etch barrier film 19. The organic anti-reflection film 27 remains between the second interlayer insulating film and the first etch barrier film 15.
Now referring to FIG. 1d, the photoresist pattern 29 and the organic anti-reflection film 27 are sequentially removed to expose the first etch barrier film 15 on the lower metal line 11.
Referring to FIG. 1e, the exposed portion of the first etch barrier film 15 is removed via an etch-back process to form an upper metal line region 31 for contacting the lower metal line 11. The etch-back process is performed without using a mask, wherein the edges of the second etch barrier film 19, the second interlayer insulating film 17, and the hard mask layer 23 are etched to have a shape denoted as ‘A’ in FIG. 1e. 
The edges having the shape denoted as ‘A’ in FIG. 1e has an effect of reducing the distance between the upper metal lines to cause shorts between the upper metal lines. The short between the upper metal lines degrades the electrical characteristic of metal lines.
FIG. 2 is a SEM photograph showing copper lines manufactured in accordance with the conventional method. As can be seen from FIG. 2, the critical dimension between the copper lines is reduced.